Fabrication of semiconductor memory devices and other semiconductor devices containing memory is an imperfect process. The imperfections in the fabrication process lead inevitably to imperfections in the semiconductor devices themselves. Such imperfections might manifest themselves as, for example, semiconductor crystalinity defects or electrical connector discontinuities. Naturally, such imperfections in the semiconductor devices can lead to errors in storing and retrieving data from memory cells contained within such semiconductor devices. For this reason, it is necessary to test each and every memory cell on a semiconductor device after fabrication and prior to selling such devices to manufacturers and other end users for use in electronic systems.
Semiconductor and memory device testing was originally only intended to identify faulty devices which were then discarded. As memory cell density has increased, however, the failure rates of devices containing memory cells can become intolerably large leading to too many devices being discarded. In an effort to improve device yields, methods for repairing defective devices have been developed. More specifically, semiconductor devices with repairable memory typically include redundant rows or columns of memory cells. During testing of such devices, the addresses of the faulty rows, columns or cells are identified and the addresses saved. These faulty memory rows, columns or cells are then effectively replaced by one of the redundant rows, columns. This is typically accomplished through the use of fuses or anti-fuses (hereinafter referred to collectively as ‘fuses’) which are used to create open and closed circuit paths within the memory or its associated decoders. Through the use of a laser, an appropriate combination of fuses can be “blown” thereby electrically isolating defective cells while electrically connecting the redundant cells in their place.
Most typically, both the testing and repair of semiconductor devices has been accomplished through the use of complex test equipment that is physically connected to each memory die. Moreover, it is not uncommon that testing of the devices is done on one piece of equipment and the repair on another. Obviously, testing, repairing and then retesting of the repaired devices takes a great deal of time when the devices have to be moved from one machine to another. To help mitigate this problem, test and repair circuitry can be built into the semiconductor device itself. Built-in self test (BIST) and built-in self repair (BISR) capabilities within semiconductor devices containing memory can increase device yields in a time efficient manner.
Validation and repair of prior art semiconductor devices using BIST and BISR still generally requires the use of a test machine. The test machine is used to electrically interface with a device die. Once the test machine is connected, the machine is used to issue a test mode command to the die. This mode is used to enable the BIST circuitry to run test patterns against the memory cells and other circuitry. When a test failure occurs, the BIST circuitry in the device captures the address of any memory failures. Once the address or addresses have been captured, the test machine issues may be used to control and direct the repair with, for example, a laser repair machine. After repair is complete, the test machine is typically used to run the test patterns again to ensure the repair was completed properly and otherwise verify the integrity of the device.
An example of a prior art repair system is illustrated in FIG. 1. A die 100 includes a memory array 140, row and column decoders 120, redundant row and column decoders 125 and a control module 110. The integrated circuit die 100 may optionally contain other logic or an application specific integrated circuit (ASIC) 145. As was described above, a Test and Repair Machine 105 interfaces directly with the integrated circuit die 100. The Test and Repair Machine 105 may, for example, run tests on the memory array 140 and related circuitry. A typical test might write data to the memory array 140 and then later read the data. A test comparator 130 would then compare the read data with the data that was written to determine if there has been an error. If so, an error flag is generated and routed to the control module 210. The error flag may be used by the control module 210 for storing the failure address within the control module 210 or elsewhere on the device. Alternatively, the error flag may be routed directly to the test and repair machine 105 and the machine 105 can store the failure address. The failure address, whether stored internally or externally, may be used to program a fuse bank in the redundant row and column decoders 125 with, for example, an external laser repair machine as was discussed above. Once the appropriate fuses have been programmed, the redundant row and column decoders 125 are able to replace a received address of the faulty memory cells with an address of redundant cells in the memory array 140.
Although this process of validation and repair has increased chip yields and testing efficiency, it is not without certain drawbacks. Most notably, the prior art repair circuitry may only be accessed at the die level by a test machine. That is, once the die has been packaged into, for example, a single inline package (SIP), the repair circuitry (e.g. a fuse) is no longer easily accessible and further repairs to the memory are not easily made. Semiconductor devices containing memory may, however, develop further faults during the packaging process or in subsequent use. The current technology does not allow for the packaged devices to be easily repaired. Memory manufacturers and customers who use the final packaged devices cannot, therefore, easily repair memory within these faulty devices. If such failures could easily be repaired after sale, customer yield would be desirably improved.
There is therefore a need for a system for accessing and controlling the repair circuitry of semiconductor devices containing memory after the devices have been packaged.